// This is a configuration file for the Sail RISC-V emulator. // // You can copy and then modify it to create a new configuration file, // and then use the `--config` option to use it with the // `sail_riscv_sim` emulator. If any CMake @VARIABLE@ placeholders // are present in this file, they will need to be replaced with valid // values. // // This file has an associated JSON Schema, which is generated by the // Sail compiler as a build artifact. See the documentation (e.g. the // top-level README) on how to get the associated schema. { "base": { "xlen": @CONFIG__BASE__XLEN@, "E": false, "writable_misa": true, "writable_fiom": true, // The top 29 bits in this value control whether the corresponding // HPM counters (hpmcounter31 .. hpmcounter3) are supported // (i.e. are not read-only zero). A set bit specifies that the // corresponding counter is supported. The lowest 3 bits // (writable_hpm_counters[2 .. 0]) are ignored. "writable_hpm_counters": { "len": 32, "value": "0xFFFF_FFFF" }, // The top 29 bits in this value control whether the // corresponding bits of the `scounteren` CSR that control HPM // counters are read-only zero. A set bit specifies that the // corresponding bit of `scounteren` is writable, otherwise // the bit is read-only zero. The lowest 3 bits are ignored. // If Sscounterenw is supported this must be a superset of // `writable_hpm_counters`. "scounteren_writable_bits": { "len": 32, "value": "0xFFFF_FFFF" }, // These settings control whether the specified exceptions // cause information to be written into the appropriate // `xtval` registers. "xtval_nonzero": { "illegal_instruction": true, "software_breakpoint": true, "hardware_breakpoint": true, "load_address_misaligned": true, "load_access_fault": true, "load_page_fault": true, "samo_address_misaligned": true, "samo_access_fault": true, "samo_page_fault": true, "fetch_address_misaligned": true, "fetch_access_fault": true, "fetch_page_fault": true, "software_check": true, "reserved_exceptions": false }, "reserved_behavior": { // The configuration option determines how to handle the reserved behavior `amocas_odd_registers`. // "AMOCAS_Fatal" – raise a Sail exception, stopping execution. // "AMOCAS_Illegal" – treat it as an illegal instruction. "amocas_odd_register": "AMOCAS_Illegal", // The configuration option determines how to handle execution of a floating-point // instruction with DYN (dynamic) rounding mode when `fcsr.FRM` contains a // reserved value (0b101, 0b110, 0b111). // This does not affect the execution of floating-point instructions that have a // reserved rounding mode statically encoded in the instruction. // "Fcsr_RM_Fatal" – raise a Sail exception, stopping execution. // "Fcsr_RM_Illegal" – treat it as an illegal instruction. "fcsr_rm": "Fcsr_RM_Illegal", // The configuration option determines how to handle the reserved behavior `pmpcfg_with_R0W1`. // "PMP_Fatal" – raise a Sail exception, stopping execution. // "PMP_ClearPermissions" – convert a PMP entry with R=0, W=1 to R=0, W=0, X=0. "pmpcfg_write_only": "PMP_ClearPermissions", // The configuration option determines how to handle the reserved behavior `xenvcfg.CBIE` with 0b10. // "Xenvcfg_Fatal" – raise a Sail exception, stopping execution. // "Xenvcfg_ClearPermissions" – convert CBIE with 0b10 to 0b00. "xenvcfg_cbie": "Xenvcfg_ClearPermissions", // The configuration option determines how to handle the reserved behavior `xtvec[Mode] >= 2`. // "Xtvec_Fatal" – raise a Sail exception, stopping execution. // "Xtvec_Ignore" – use old Mode of xtvec. "xtvec_mode": "Xtvec_Ignore", // The configuration option determines how to handle the reserved behavior: Odd-numbered registers for RV32Zdinx. // "Zdinx_Fatal" – raise a Sail exception, stopping execution. // "Zdinx_Illegal" – treat it as an illegal instruction. "rv32zdinx_odd_register": "Zdinx_Illegal" } }, "memory": { "pmp": { "grain": 0, // This specifies the number of PMP entries present. // The value must be one of 0, 16, or 64. "count": 16, // This specifies the number of usable PMP entries. // Entries higher than this are read-only-zero. // The value must be less than or equal to `count`. "usable_count": 16, "tor_supported": true, "na4_supported": true, "napot_supported": true }, // These settings control global support for misaligned access so they are // checked before address translation. `misaligned_fault` in // `regions` is checked after address translation. "misaligned": { // If this is false then all misaligned accesses will raise a misaligned exception. "supported": true, // Memory accesses that span multiple naturally aligned // 2^allowed_within_exp sized regions will be split into multiple // memory operations. 0 means all misaligned accesses will be split. // The maximum value is 12 (one page). "allowed_within_exp": 0, // If the access gets split due to `allowed_within_exp` then the size // of the operations will be one byte if `byte_by_byte` is set, otherwise // they will be the maximum size possible based on the alignment. For // example a 4-byte access to address 0x2 will use two 2-byte operations. "byte_by_byte": false, // If multiple memory operations are needed, this controls whether they // are done in increasing or decreasing address order. This is architecturally // observable because some store operations may succeed, and even for // loads the resulting `xtval` may depend on this setting. "order_decreasing": false }, // Address to write DTB to (if provided). "dtb_address": { "len": 64, "value": "0x1000" }, // The locations and sizes of memory regions and their PMAs. These regions // are required to be aligned to 4K (page) boundaries. "regions": [ // ROM { "base": { "len": 64, "value": "0x1000" }, "size": { "len": 64, "value": "0x1000" }, "attributes": { "mem_type" : "IOMemory", "cacheable": true, "coherent": false, "executable": false, "readable": true, "writable": false, "read_idempotent": true, "write_idempotent": true, "misaligned_fault": "NoFault", "atomic_support": "AMONone", "reservability": "RsrvNone", "supports_cbo_zero": false, "supports_pte_read": false, "supports_pte_write": false }, "include_in_device_tree": false }, // MMIO { "base": { "len": 64, "value": "0x2000000" }, "size": { "len": 64, "value": "0x10000000" }, "attributes": { "mem_type": "IOMemory", "cacheable": false, "coherent": true, "executable": false, "readable": true, "writable": true, "read_idempotent": false, "write_idempotent": false, "misaligned_fault": "AlignmentFault", "atomic_support": "AMONone", "reservability": "RsrvNone", "supports_cbo_zero": false, "supports_pte_read": false, "supports_pte_write": false }, "include_in_device_tree": false }, // RAM { "base": { "len": 64, "value": "0x80000000" }, "size": { "len": 64, "value": "0x80000000" }, "attributes": { "mem_type": "MainMemory", "cacheable": true, "coherent": true, "executable": true, "readable": true, "writable": true, "read_idempotent": true, "write_idempotent": true, "misaligned_fault": "NoFault", "atomic_support": "AMOCASQ", "reservability": "RsrvEventual", "supports_cbo_zero": true, "supports_pte_read": true, "supports_pte_write": true }, "include_in_device_tree": true } ] }, "platform": { "vendorid": 0, "archid": 0, "impid": 0, "hartid": 0, // Cache block size, specified as a power of 2. "cache_block_size_exp": 6, // This specifies both the size and alignment of the reservation set, specified as a power of 2. // It must be at least 2 on RV32 and 3 on RV64 to support Zalrsc. It must not be more than // 6 for Za64rs and 7 for Za128rs. In all cases, it must be less than or equal to 12. "reservation_set_size_exp": 3, "clint": { // This must be in a suitable memory region (see `memory.regions`). "base": 33554432, "size": 786432 }, // Very simple MMIO device to generate interrupts for testing // purposes. See docs/SimpleInterruptGenerator.md for details. "simple_interrupt_generator": { // This must be in a suitable IO memory region (see `memory.regions`) // and 4-byte aligned. The size is always 0x20. "base": 201326592 }, "clock_frequency": 1000000000, "instructions_per_tick": 2, "wfi_is_nop": false, // The maximum increment in the time CSR before a wait instruction // (e.g. WFI, WRS.NTO, WRS.STO) that is not a NOP expires its // wait. It is not possible to wait indefinitely. // // If WFI or WRS.STO (Short TimeOut) exceed this limit in // non-machine privilege with mstatus[TW] set, an illegal // instruction is raised. Otherwise they retire successfully. // // Note: it is also legal for these instructions to spuriously // retire successfully at any point, but there is currently no // configuration option for this behaviour. "max_time_to_wait": 10 }, "extensions": { "M": { "supported": true }, "A": { "supported": true }, "F": { "supported": true }, "D": { "supported": true }, "V": { // `support_level` must be one of the below strings: // . "Disabled" for no vector extension support // . "Integer" for Zve*x support // . "Float_single" for Zve*f support // . "Float_double" for Zve*d support // . "Full" for the full V extension // Note that `support_level` requires compatible // values for `vlen_exp` and `elen_exp` below. // For e.g. Zve32x and Zve32f require `elen_exp` >= 5, // Zve64x, Zve64f, and Zve64d require `elen_exp` >= 6, // and V requires `elen_exp` >= 6 and `vlen_exp` >= 7. "support_level": "@CONFIG__V__SUPPORT@", "vlen_exp": @CONFIG__V__VLEN_EXP@, "elen_exp": @CONFIG__V__ELEN_EXP@, "vl_use_ceil": false }, "B": { "supported": true }, "S": { "supported": true }, "U": { "supported": true }, "Zibi": { "supported": true }, // This extension just asserts that the cache block size is 64 bytes. // If you enable this you also need to ensure `platform.cache_block_size_exp` // is 6, otherwise you will get a config validation error. "Zic64b": { "supported": true }, "Zicbom": { "supported": true }, "Zicbop": { "supported": true }, "Zicboz": { "supported": true }, "Ziccamoa": { "supported": true }, "Ziccamoc": { "supported": true }, "Ziccrse": { "supported": true }, "Zicfilp": { "supported": true }, "Zicfiss": { "supported": true }, "Zicond": { "supported": true }, "Zicntr": { "supported": true }, "Zicsr": { "supported": true }, "Zifencei": { "supported": true }, "Zihintntl": { "supported": true }, "Zihintpause": { "supported": true }, "Zihpm": { "supported": true }, "Zimop": { "supported": true }, "Zmmul": { "supported": false }, "Zaamo": { "supported": false }, "Zabha": { "supported": true }, "Zacas": { "supported": true }, "Zalrsc": { "supported": false }, "Zawrs": { "supported": true, "nto": { "is_nop": false }, "sto": { "is_nop": false } }, "Zfa": { "supported": true }, "Zfbfmin": { "supported": true }, "Zfh": { "supported": true }, "Zfhmin": { "supported": true }, "Zfinx": { "supported": false }, "Zdinx": { "supported": false }, "Zca": { "supported": true }, "Zcf": { "supported": @CONFIG_XLEN_IS_32@ }, "Zcd": { "supported": true }, "Zcb": { "supported": true }, "Zcmop": { "supported": true }, "Zba": { "supported": false }, "Zbb": { "supported": false }, "Zbs": { "supported": false }, "Zbc": { "supported": true }, "Zbkb": { "supported": true }, "Zbkc": { "supported": true }, "Zbkx": { "supported": true }, "Zknd": { "supported": true }, "Zkne": { "supported": true }, "Zknh": { "supported": true }, "Zkr": { "supported": true, "sseed_reset_value": false, "useed_reset_value": false, "sseed_read_only_zero": false, "useed_read_only_zero": false }, "Zksed": { "supported": true }, "Zksh": { "supported": true }, "Zkt": { "supported": true }, "Zhinx": { "supported": false }, "Zhinxmin": { "supported": false }, "Zvabd": { "supported": true }, "Zvfbfmin": { "supported": true }, "Zvfbfwma": { "supported": true }, "Zvfh": { "supported": true }, "Zvfhmin": { "supported": true }, "Zvbb": { "supported": true }, "Zvbc": { "supported": @CONFIG_ELEN_IS_64@ }, "Zvkb": { "supported": false }, "Zvkg": { "supported": true }, "Zvkned": { "supported": true }, "Zvknha": { "supported": true }, "Zvknhb": { "supported": @CONFIG_ELEN_IS_64@ }, "Zvksed": { "supported": true }, "Zvksh": { "supported": true }, "Zvkt": { "supported": true }, "Ssccptr": { "supported": true }, "Sscofpmf": { "supported": true }, "Sscounterenw": { "supported": true }, "Sstc": { "supported": true }, // Enabling Sstvala requires that the exceptions specified in the extension // have their appropriate settings under `base.xtval_nonzero`. "Sstvala": { "supported": true }, "Svade": { "supported": true }, "Svadu": { "supported": true }, "Svinval": { "supported": true }, "Svrsw60t59b": { "supported": @CONFIG_XLEN_IS_64@ }, "Svnapot": { "supported": @CONFIG_XLEN_IS_64@ }, "Smcntrpmf": { "supported": true }, "Svbare": { "supported": true, "sfence_vma_illegal_if_svbare_only": true }, "Sv32": { "supported": @CONFIG_XLEN_IS_32@ }, "Sv39": { "supported": @CONFIG_XLEN_IS_64@ }, "Sv48": { "supported": @CONFIG_XLEN_IS_64@ }, "Sv57": { "supported": @CONFIG_XLEN_IS_64@ }, "Stateen": { "Smstateen": { "supported": true }, "Ssstateen": { "supported": true }, "C_readonly_zero": true, "SE0_readonly_zero": false }, "Ssqosid": { "supported": true, "rcid_length": 12, "mcid_length": 12 }, "Svpbmt": { "supported": @CONFIG_XLEN_IS_64@ }, "Svvptc": { "supported": true } } }