代码库
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
SystemVerilog
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
SystemVerilog
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
SystemVerilog