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README.md
Learn RISC-V
A community-driven, continuously updated compilation of RISC-V learning resources. Content is organized by topic and experience level to help you discover courses, software, documentation, and articles efficiently.
RISC-V is an open standard Instruction Set Architecture (ISA) based on established Reduced Instruction Set Computer (RISC) principles.
👋 Want to learn about RISC-V? Check out the Beginner-Level or Intermediate-Level learning resources.
Star History
👉 Table of Contents
➕ Making Contributions
We love contributions! Check out contributing.md for more info. Thank you for your interest in contributing to our RISC-V tutorial compilation.
📙 Resources
Learning Resources for RISC-V
🟢 Beginner-Level Resources
For those with little or no knowledge of digital logic design. Consider starting with Digital Design & Computer Architecture (RISC-V Edition) and then progressing to intermediate-level courses like RVfpga.
| Resource | Author(s) | Description | Access | Date Added |
|---|---|---|---|---|
| An Introduction to Assembly Programming with RISC-V | Prof. Edson Borin | Teaches RISC-V assembly programming concepts. | Webpage | 2024-05-03 |
| Architecture 1005: RISC-V Assembly | OpenSecurityTraining | Security-focused exploration of RISC-V ISAs and extensions. | Course videos | 2024-04-15 |
| Basic Computer Architecture | Smruti R. Sarangi | Computer architecture fundamentals. | Website | 2024-12-27 |
| Computer Architecture Basics | CTU Prague – FEE (Pavel Piša) | Course covering computer architecture basics, including CPU design and speculative execution. | Course videos | 2024-04-16 |
| Creating a RISC-V from scratch! | Lucas Teske (Teske's Lab) | Learning livestream series focused on creating an RV32E that runs on FPGAs. | YouTube (Portuguese) | 2024-10-18 |
| Digital Design & Computer Architecture RISC-V Edition | Sarah L. Harris, David M. Harris | Foundational digital logic design and RISC-V processor implementation. | Amazon | 2024-10-01 |
| Easy RISC-V | Vivian “dramforever” Wang | RISC-V assembly tutorial with interactive emulator (RV32I and some privileged arch). | Webpage | 2025-10-30 |
| Hands-on RISC-V Processor Design | Rahul Behl | Dive into RISC-V processor design using SystemVerilog. | QuickSilicon | 2024-10-01 |
| learn-FPGA episode I: from blinky to RISC-V | Bruno Levy | Design an FPGA-based RISC-V softcore starting from a basic Verilog blinker. | GitHub | 2024-10-01 |
| LinuxFoundationX: Building a RISC-V CPU Core | Steve Hoover | Free course on RISC-V microarchitecture design using open-source tools. | edX course | 2024-10-01 |
| Nand2Tetris | Noam Nisan, Shimon Schocken | Build a computer from logic gates using a hardware simulator. | Website | 2024-10-01 |
| RISC-V Assembly Introduction (Portuguese) | Gabriel G. de Brito | Basics of RISC-V IM architecture with the EGG emulator. | Course videos | 2024-06-04 |
| Step-by-step RISC-V Compiler Development | Shao-Ce Sun | Practical guide to RISC-V C compiler development. | Teaching resources · Course videos (Chinese) | 2024-03-20 |
| Step-by-step RISC-V OS Development | Chen Wang | Practical guide for developing RISC-V operating systems. | Teaching resources · Course videos (Chinese) | 2024-05-03 |
| The RISC-V Reader: An Open Architecture Atlas | David Patterson, Andrew Waterman | Introduction to the RISC-V instruction set. | RISC-V Reader | 2024-05-03 |
| Writing a RISC-V OS From Scratch | Seiya Nuta | Write an OS for RISC-V in about 1,000 lines of code. | Webpage | 2025-07-27 |
| Why Your Phone Is So Fast: The Sports Car vs. The Truck | David Patterson | How do we keep making computers faster? | Webpage | 2025-02-09 |
🔵 Intermediate-Level Resources
Advanced materials for learners familiar with digital logic and basic architecture.
| Resource | Author(s) | Description | Access | Date Added |
|---|---|---|---|---|
| Computer Architecture: A Quantitative Approach (6th Edition) | David Patterson, John Hennessy | Advanced topics including ILP and GPU architectures, using RISC-V. | Amazon | 2024-10-01 |
| Computer Organization & Design (RISC-V Edition) | David Patterson, John Hennessy | In-depth study of RISC-V ISA and processor implementation. | Amazon | 2024-10-01 |
| HaDes-V | Tobias Scheipel | The Instruction Guide and code template (OER) for microcontroller design using the HaDes-V RISC-V-based processor. | GitHub · Instruction Guide | 2024-12-18 |
| Learn with SHAKTI | Shakti – RISE Lab, IITM | Tutorials on RISC-V assembly programming using the RISC-V toolchain. | Learn with Shakti | 2023-12-21 |
| learn-FPGA episode II: pipelining | Bruno Levy | Extends the basic RISC-V softcore from episode I with pipelining and performance optimizations. | GitHub | 2024-10-01 |
| LinuxFoundationX: RISC-V Toolchain and Compiler Optimization Techniques | Aditya Kumar | RISC-V toolchain internals and compiler optimizations. | edX course | 2024-10-01 |
| RISC-V Optimization Guide | RISE Project | Actionable optimization recommendations for RISC-V software developers. | GitLab | 2024-02-19 |
| RV64GC Linker from Scratch in Go | Yang Liu, PLCT Lab | Build an RV64GC linker from scratch in Go. | GitHub · Course videos (Chinese) | 2024-04-24 |
| RVfpga (Extended): Understanding Computer Architecture | Sarah Harris, Daniel Chaver-Martinez | Updated RVfpga course with FPGA and simulation tools. | RVfpga v3.0 downloads | 2024-06-02 |
| RVfpga: Computer Architecture with an Industrial RISC-V Core | Sarah Harris, Daniel Chaver-Martinez | Hands-on learning with a commercial RISC-V SoC on FPGAs. | edX course | 2024-10-01 |
| Teaching experiences with RVfpga | ARTECS Group, Complutense University of Madrid | How RVfpga and the Ripes simulator were used in two UCM courses. | GitHub | 2024-10-18 |
| Tutorial: RISC-V Vector Extension Demystified | Thang Tran | In-depth introduction to the RISC-V vector extension. | YouTube | 2024-10-01 |
| Tutorial: basic_RV32s | T410N | A systematic microarchitectural roadmap for learning RISC-V processor design from scratch. | basic_RV32s | 2024-07-25 |
| RISC-V Vector Primer | Tran, Thang Minh and Miller, Paul and McLeod, Jonah | A structured, open technical primer explaining the RISC‑V Vector Extension, with examples, diagrams, and chapter‑based documentation. | GitHub | 2026-02-07 |
Software and Tools
Tools to enhance understanding or visualize the RISC-V ISA.
| Tool | Author(s) | Description | Access | Date Added |
|---|---|---|---|---|
| CREATOR | Diego Camarmas Alonso, Félix García Carballeira, Alejandro Calderón Mateos, Elías del Pozo Puñal | Didactic simulator for RISC-V assembly programs. | Website | 2023-12-20 |
| emulsiV | Guillaume Savaton | Visual simulator for a minimal 32-bit RISC processor. | Website | 2023-12-20 |
| Go RISC-V Emulator | Lucas Teske | A Go implementation of RV32I+M that can run Doom. | GitHub | 2024-10-18 |
| Compiler Explorer | Matt Godbolt | Online compiler explorer supporting GCC/LLVM for RV64. | Website | 2024-10-18 |
| Online RISC-V Assembler | Lucas Teske | Online RISC-V assembler using GNU assembler in WebAssembly. | Website, GitHub | 2024-10-18 |
| Piscado | Gustavo N. Martins | RISC-V simulator written in Python during Twitch live coding. | GitHub | 2024-10-18 |
| QtRvSim | CTU Prague | RISC-V simulator with cache and pipeline visualization. | GitHub | 2023-12-20 |
| RISC-V ALE | Antonio Guimarães | RISC-V Assembly Learning Environment. | Website | 2024-10-18 |
| RISC-V Instruction Encoder/Decoder | LupLab | Online tool for encoding/decoding RISC-V instructions. | Website | 2023-12-20 |
| Risco-5S | Julio Nunes Avelar | RISC-V simulator with RV32IM, built during a few days off. | GitHub | 2023-11-04 |
| RVV Intrinsics Viewer | dzaima | Documentation for RISC-V vector extension intrinsics. | Website | 2023-12-20 |
| WebRISC-V | Roberto Giorgi, Gianfranco Mariotti | Web-based graphical simulation with pipeline visualization for RV32IM/RV64IM. | GitHub | 2025-08-14 |
Open RISC-V Implementations
Explore open RISC-V implementations for hands-on learning.
| Name | Description | Access | Date Added |
|---|---|---|---|
| AUK-V-Aethia | AUK-V RV32I CPU. | GitHub | 2024-10-18 |
| CV32E40P | In-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY (PULP-Platform). | GitHub | 2024-10-18 |
| CVA6 | CORE-V CVA6, an application-class 6-stage RISC-V CPU capable of booting Linux. | GitHub | 2024-10-18 |
| DarkRISCV | Small RV32-E/I soft-core CPU optimized for FPGAs. | GitHub | 2024-10-18 |
| Didactic-RISC-V | Didactic RV32I Zmmul Zicsr implementation with 3-stage pipeline, in Logisim Evolution and SystemVerilog. | GitHub | 2026-03-24 |
| Grande Risco-5 | RV32I multi-cycle processor with a 5-stage pipeline for education. | GitHub | 2024-11-06 |
| Hazard3 | 3-stage RV32IMACZb* processor with debug. | GitHub | 2024-12-19 |
| KianV | SV32 (MMU) RV32IMA Zicntr Zicsr Zifencei SSTC Linux/XV6 ASIC/FPGA SoC. | GitHub | 2025-09-30 |
| Kronos | 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA. | GitHub | 2024-10-18 |
| Leaf | Small RV32I SoC in VHDL for portable applications; FPGA and ASIC. | GitHub | 2024-10-23 |
| Maestro | 5-stage pipeline RV32I implementation in VHDL. | GitHub | 2024-10-18 |
| Mriscv | 32-bit microcontroller featuring a RISC-V core. | GitHub | 2024-10-18 |
| NEORV32 | MCU-class RISC-V soft-core CPU, customizable and extensible. | GitHub | 2024-11-01 |
| NERV | Naive Educational RISC-V processor. | GitHub | 2024-10-18 |
| NoX | Small RISC-V (RV32I) core written in SystemVerilog. | GitHub | 2024-10-21 |
| Pequeno | Pipelined in-order RISC-V CPU core compliant with RV32I. | GitHub | 2023-12-20 |
| PicoRV32 | Size-optimized RISC-V CPU. | GitHub | 2024-10-18 |
| ReonV | Modified LEON3 (SPARC V8) to RISC-V ISA, VHDL. | GitHub | 2024-10-18 |
| Riscado-V | Simple RISC-V (RV32I) implementation in Verilog. | GitHub | 2024-10-18 |
| Risco-5 | Multi-cycle RISC-V processor with RV32I/E[M]. | GitHub | 2024-10-18 |
| RISC-V Steel | RV32I + Zicsr + Machine mode. | GitHub | 2024-10-18 |
| RISCV-CPU | 6-stage pipelined RV32IM+Zicsr+Zifencei processor in SystemVerilog on Xilinx Zynq-7020 FPGA, with branch prediction (BHT/BTB/RAS), hardware multiplier/divider, UART subsystem, and full hazard handling. 263.7 CoreMark / 91.0 DMIPS at 100 MHz. | GitHub | 2026-03-24 |
| RPU | Basic RISC-V CPU in VHDL. | GitHub | 2024-10-18 |
| RSD | RISC-V out-of-order superscalar processor. | GitHub | 2024-10-18 |
| SERV | The SErial RISC-V CPU. | GitHub | 2024-10-18 |
| SGDH-RVSoC | Tiny 32-bit RISC-V rv32acim CPU capable of running Linux on FPGA and in simulation. | GitHub | 2025-10-08 |
| TinyRiscv | Very simple and easy-to-understand RISC-V core. | GitHub | 2024-10-18 |
| VestaRV | RV32IMACZb* synthesizable mixed-signal MCU SoC for ASIC and FPGA. Includes HDL sources, User Guide, RISC-V ISA verification suite, and simulation instructions. Fabricated and silicon-verified as the 'Myshkin' ASIC (TSMC 65nm, Nov 2025). | GitHub | 2026-03-24 |
| VexRiscv | FPGA-friendly 32-bit RISC-V CPU (SpinalHDL). | GitHub | 2024-10-18 |
| Riskow | Toy RV32-E from scratch during livestreams; runs on low-cost FPGAs. | GitHub | 2024-10-18 |
Available RISC-V Boards, Development Kits, Tablets, and Laptops
🟢 32-bit Hardware
Popular hardware based on RV32 processors.
| Board or Dev Kit | Company | SoC | RISC-V Core | Frequency | Date Added |
|---|---|---|---|---|---|
| CH32V003 Devkit | WCH | CH32V003 | Single-core QingKe V2A | 48 MHz | 2025-07-25 |
| ESP32C2 Devkit | Espressif | ESP32C2 | Single-core 32-bit | 120 MHz | 2025-07-25 |
| ESP32C3 Devkit | Espressif | ESP32C3 | Single-core 32-bit | 160 MHz | 2025-07-25 |
| ESP32C5 Devkit | Espressif | ESP32C5 | Single-core 32-bit | 240 MHz | 2025-07-25 |
| ESP32C6 Devkit | Espressif | ESP32C6 | Single-core 32-bit | 160 MHz | 2025-07-25 |
| ESP32H2 Devkit | Espressif | ESP32H2 | Single-core 32-bit | 96 MHz | 2025-07-25 |
| ESP32P4 EV Board | Espressif | ESP32P4 | Dual-core 32-bit | 360 MHz | 2025-07-25 |
| Longan Nano | Sipeed | GD32VF103CBT6 | Single-core 32-bit | 108 MHz | 2025-07-25 |
| M0sense | Sipeed | BL702 | Single-core 32-bit | 144 MHz | 2025-08-24 |
| Raspberry Pi Pico 2 | Raspberry Pi | RP2350 | Dual-core Hazard3 | 150 MHz | 2024-12-19 |
Following are no longer available:
| Board or Dev Kit | Company | SoC | RISC-V Core | Frequency | Date Added |
|---|---|---|---|---|---|
| HiFive1 | SiFive | FE310-G000 | 32-bit E31 | 256 MHz | 2024-10-31 |
| HiFive1 Rev B | SiFive | FE310-G002 | 32-bit E31 | 256 MHz | 2024-10-31 |
🔵 64-bit Hardware
Popular hardware based on RV64 processors.
| Board or Dev Kit | Company | SoC | RISC-V Core | Date Added |
|---|---|---|---|---|
| Banana Pi F3 | Banana Pi | SpacemiT K1 | Octa-core X60 | 2024-11-01 |
| BeagleV-Ahead | BeagleBoard.org | TH1520 | T-HEAD quad-core Xuantie C910 | 2025-07-26 |
| BeagleV-Fire | BeagleBoard.org | Microchip PolarFire MPFS025T | 4× RV64GC + 1× RV64IMAC | 2025-07-26 |
| DC Roma Laptop I | DeepComputing | StarFive JH7110 | Quad-core | 2025-11-03 |
| DC Roma Laptop II | DeepComputing | SpacemiT K1 | Octa-core X60™ | 2024-10-31 |
| DC Roma Mainboard I | DeepComputing | StarFive JH7110 | Quad-core | 2025-11-03 |
| DC Roma Mainboard II (AI PC) | DeepComputing | ESWIN EIC7702X | SiFive octa-core P550 | 2025-07-25 |
| HiFive Premier P550 | SiFive | ESWIN EIC7700X | SiFive quad-core P550 | 2024-10-31 |
| HiFive Unmatched | SiFive | SiFive U74-MC | 64-bit S7 | 2024-10-31 |
| Kendryte K230 | Canaan Technology | K230 | Dual-core T-HEAD C908 | 2024-11-01 |
| LicheeBook 4A | Sipeed | TH1520 | Quad-core T-HEAD C910 | 2024-10-31 |
| LicheePi 3A | Sipeed | SpacemiT K1 | Octa-core X60 | 2024-10-31 |
| LicheePi 4A | Sipeed | TH1520 | Quad-core T-HEAD C910 | 2024-10-31 |
| LicheePi Console 4A | Sipeed | TH1520 | Quad-core T-HEAD C910 | 2024-10-31 |
| LicheeRV D1 | Sipeed | AllWinner D1 | Single-core T-HEAD C906 | 2024-10-31 |
| LicheeRV Nano | Sipeed | SG2002 | Single-core T-HEAD C906 | 2024-10-31 |
| MangoPi MQ-Pro | MangoPi | D1 | Single-core T-HEAD C906 | 2025-07-28 |
| Milk-V Duo | Milk-V | CV1800B | T-HEAD C906 | 2024-10-31 |
| Milk-V Duo256M | Milk-V | SG2002 | T-HEAD C906 | 2024-10-31 |
| Milk-V Duo S | Milk-V | SG2000 | T-HEAD C906 | 2024-10-31 |
| Milk-V Jupiter | Milk-V | SpacemiT K1 | Octa-core X60 | 2024-10-31 |
| Milk-V Mars | Milk-V | JH7110 | Quad-core SiFive U74 | 2024-10-31 |
| Milk-V Meles | Milk-V | TH1520 | Quad-core T-HEAD C910 | 2024-10-31 |
| Milk-V Pioneer | Milk-V | SG2042 | 64 cores T-HEAD C910 | 2024-10-31 |
| Milk-V Vega | Milk-V | FSL1030M | UX608 core | 2024-10-31 |
| OK7110-C | Forlinx | JH7110 | Quad-core SiFive U74 | 2024-10-31 |
| Ox64 | Pine64 | BL808 | T-HEAD C906, E907, E902 | 2024-10-31 |
| PineTab-V | Pine64 | JH7110 | Quad-core SiFive U74 | 2024-10-31 |
| SpacemiT MUSE Book | SpacemiT | SpacemiT K1 | Octa-core X60 | 2025-09-04 |
| SpacemiT MUSE Box | SpacemiT | SpacemiT K1 | Octa-core X60 | 2025-09-04 |
| SpacemiT MUSE Card | SpacemiT | SpacemiT M1 | Octa-core X60 | 2025-09-02 |
| SpacemiT MUSE Pi | SpacemiT | SpacemiT M1 | Octa-core X60 | 2024-11-01 |
| SpacemiT MUSE Pi Pro | SpacemiT | SpacemiT M1 | Octa-core X60 | 2025-09-02 |
| Star 64 | Pine64 | JH7110 | Quad-core SiFive U74 | 2024-10-31 |
| VisionFive 2 | StarFive Technology | JH7110 | Quad-core SiFive U74 | 2024-10-31 |
Articles and Presentations
| Resource | Author(s) | Description | Access |
|---|---|---|---|
| Design of the RISC-V Instruction Set Architecture | Andrew Waterman | PhD dissertation on the structure of the RISC-V ISA. | |
| Is RISC-V the Future? | Roddy Urquhart | Examination of RISC-V’s future potential. | Article |
| Past, Present and Future of RISC-V | Krste Asanović | Overview of RISC-V’s evolution. | YouTube |
| x264 SAD Optimization with RISC-V Vector | Fernando Mendoza V., Thomas Kolman | Optimizing the Sum of Absolute Differences (SAD) function in x264 using the RISC-V Vector 1.0 extension for the RVA23 profile, achieving up to 4x speedup over scalar C code. |